Sr Staff ASIC Verification Engineer

Company Overview

Role Profile

What You’ll Be Doing

• Own verification for a major IP block, subsystem, or cross-IP methodology through final signoff and customer delivery.
• Define verification strategy, planning, architecture, and signoff criteria for complex IP projects, including Ethernet and USB protocols.
• Lead technical execution by setting objectives, tracking milestones, managing risk, and driving coverage and quality closure.
• Apply AI-assisted methods to debug, regression analytics, test generation, and coverage closure.
• Build reusable verification infrastructure, UVM environments, and scalable methodology improvements.
• Mentor verification engineers on test planning, debug, coverage analysis, and verification best practices.
• Collaborate with design, architecture, firmware, and quality teams to align deliverables with project goals.

Expected Impact

• Deliver thoroughly verified, customer-ready DesignWare IP and reduce integration risk for silicon teams.
• Improve coverage closure, regression cycle time, debug time, and escaped-defect rates.
• Advance reusable verification infrastructure and methodologies across IP projects.
• Strengthen the verification organization through mentoring and scalable best practices.
• Identify verification gaps early and ensure robust signoff criteria before release.

What You’ll Need

• BS or BE in Electrical or Electronics Engineering with 8 or more years of IP or SoC verification experience, or MS with 6 or more years.
• Demonstrated ownership of verification for complex IP blocks, subsystems, or cross-project methodologies.
• Ability to lead verification teams and projects through technical influence and collaboration.
• Deep hands-on expertise in UVM, VMM, or OVM methodologies at unit and system levels.
• Strong proficiency in SystemVerilog, VCS or similar industry-standard simulators, and associated debug tools.

Posting Details