Layout Design, Staff Engineer
Role Overview
Own custom memory layouts for IP used in semiconductor products, from floorplanning through final signoff.
The posting states the role is not remote eligible.
Key Skills for This Role
Full Job Posting
About Synopsys
Synopsys provides engineering solutions spanning silicon to systems, including silicon design, IP, simulation, analysis, and design services.
Role overview
Own custom memory layouts for IP used in semiconductor products, from floorplanning through final signoff.
The posting states the role is not remote eligible.
Layout design and verification
- Design SRAM, Register File, ROM, and memory compiler IP layouts.
- Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools.
- Drive memory compiler technology-node migrations and resolve issues related to new process rules.
- Work with circuit designers to preserve schematic-layout correlation, matching, symmetry, and design intent.
Methodology and collaboration
- Improve layout methodologies, automation scripts, and best practices.
- Review junior engineers' layouts and provide guidance and mentoring.
- Support customer-specific memory customization and deliver production-ready IP.
- Collaborate with circuit and CAD teams; contribute layout insights to architecture and tool development.
Education and experience
- Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field.
- 8 to 10 years of hands-on custom memory layout design experience in SRAM, Register Files, ROM, or memory compiler development.
Technical qualifications
- Strong proficiency with Cadence Virtuoso or an equivalent custom layout platform.
- Expertise in DRC/LVS closure, device matching and symmetry, and analog or custom layout techniques.
- Understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes.
- Experience with parasitic extraction and physical verification flows.
- Tcl, Perl, or Python scripting for layout automation is a strong plus.
Role impact
The work supports memory IP for automotive, mobile, AI, and data center products and helps improve design cycles and prepare IP for next-generation technology nodes.
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