Senior Staff Analog Layout Engineer
Role Overview
Design and deliver analog layouts for Synopsys UCIe PHY IP used in chiplet-based products.
Work across circuit design, package engineering, digital integration, and reliability teams.
The role emphasizes chiplet architectures, 2.5D integration, advanced packaging, and UCIe die-to-die interfaces.
Key Skills for This Role
Full Job Posting
Role overview
Design and deliver analog layouts for Synopsys UCIe PHY IP used in chiplet-based products.
Work across circuit design, package engineering, digital integration, and reliability teams.
The role emphasizes chiplet architectures, 2.5D integration, advanced packaging, and UCIe die-to-die interfaces.
Responsibilities
- Design full-custom analog layouts for UCIe PHY transmitters, receivers, drivers, equalizers, DLLs, bias circuits, calibration engines, and regulators.
- Execute PHY-level floor planning, bump planning, micro bump architecture, and channel routing with package co-design.
- Implement high-speed differential routing with length matching, skew control, shielding, symmetry, and signal-integrity optimization.
- Drive physical verification closure, including DRC, LVS, ERC, antenna, density, LPE, EM/IR, and reliability checks.
- Integrate layouts with ASIC physical design flows, generate LEFs, support place-and-route, and resolve integration issues.
- Develop methodologies, automation scripts, and reusable flows; lead reviews, mentor engineers, and drive tape-out execution.
Requirements
- Diploma or bachelor's degree in Electrical Engineering, Electronics Engineering, or a related technical field.
- 8 to 15 years of hands-on analog or mixed-signal custom IC layout experience.
- Proven UCIe PHY, high-speed SerDes, or die-to-die interface IP layout experience with successful tape-outs.
- Expertise in micro bump planning, bump maps, package-aware floor planning, and 2.5D/3D die/package co-design, including interposers, RDL, and TSVs.
- Strong high-speed differential routing skills, including length matching, skew control, shielding, symmetry, and signal-integrity-driven layout.
- Experience closing DRC, LVS, ERC, EM/IR, antenna, density, and reliability checks through advanced-node tape-out.
- Experience integrating analog layouts with ASIC physical design flows.
Role impact
Layouts and bump architectures will support UCIe die-to-die interfaces and integration with digital logic, package substrates, and interposers.
Signal-integrity work affects high-speed channel performance in silicon; verification methods and automation aim to accelerate tape-out and reduce respins.
Apply for this job in 1 click
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
More jobs at Synopsys
Product Management , Staff
Vancouver, CAN
Synopsys is seeking a product manager for its photonics design and simulation software portfolio, including OptoCompiler and Lumerical. The role owns product strategy, customer discovery, roadmap prioritization, launches
R&D Engineering, Sr Engineer
, IND
Synopsys seeks a Senior Engineer to build production-grade agentic AI applications for semiconductor engineering workflows. Candidates need 2+ years of production software experience, Python proficiency, and hands-on exp
Hardware Validation Senior Engineering Manager
Mississauga, CAN
Synopsys is seeking an experienced engineering manager to lead hardware development for silicon validation. The role covers high-speed PCB design, simulation, lab debugging, and team development; candidates need extensiv
Validation / Verification Eng, Manager - 18754
Nepean, CAN
Synopsys seeks a hands-on manager to lead silicon validation of memory interface IP in its Nepean lab. The role combines first-silicon bring-up, electrical characterization, debug, test automation, and team management. C
Layout Design, Staff Engineer
, IND
Synopsys is seeking an experienced custom memory layout engineer to own SRAM, Register File, ROM, and memory compiler IP layouts through signoff. Candidates need substantial custom memory layout experience, strong physic
Staff Digital Verification Engineer
, IND
Synopsys seeks an experienced digital verification engineer to lead verification of DesignWare IP, including PHY blocks and interface logic. The role requires 4+ years of hands-on verification experience, SystemVerilog/U
R&D Engineering, Sr Engineer
, IND
Synopsys is seeking a senior engineer to characterize and model standard cell libraries for advanced technology nodes. The role requires hands-on library characterization and Liberty modeling experience, alongside knowle
R&D Engineering, Sr Engineer
, IND
Synopsys seeks a senior engineer to design and validate embedded memory circuits for production semiconductor products. The role focuses on SRAM, ROM, and register files, with a degree in a related field and 1–3 years of
Product Management , Staff
Vancouver, CAN
R&D Engineering, Sr Engineer
, IND
Hardware Validation Senior Engineering Manager
Mississauga, CAN
Validation / Verification Eng, Manager - 18754
Nepean, CAN
Layout Design, Staff Engineer
, IND
Staff Digital Verification Engineer
, IND
R&D Engineering, Sr Engineer
, IND
R&D Engineering, Sr Engineer
, IND