R&D Engineering, Sr Engineer
Role Overview
Characterize and model standard cell libraries for advanced technology nodes.
The work requires ownership of characterization flows, investigation of correlation gaps, and attention to model quality and corner cases.
Key Skills for This Role
Full Job Posting
Company and impact
Synopsys provides engineering solutions spanning silicon design, IP, simulation, analysis, and design services.
The characterized libraries support advanced-node designs and real tapeouts, helping improve timing closure, predictability, and library quality.
Role overview
Characterize and model standard cell libraries for advanced technology nodes.
The work requires ownership of characterization flows, investigation of correlation gaps, and attention to model quality and corner cases.
What you will do
- Generate Liberty models including NLDM, NLPM, CCS timing and noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and EM models.
- Debug characterization, static timing analysis, and SPICE correlation issues and identify root causes.
- Run QA checks, regression analysis, release validation, sanity testing, and model validation against design-rule checks.
- Improve and automate characterization flows; coordinate schedules, deliverables, and cross-functional status.
- Support releases with complete and accurate documentation.
What you will need
- Bachelor's or Master's in Electronics, VLSI, Microelectronics, or a related technical field.
- At least two years of hands-on standard cell library characterization and Liberty modeling experience.
- Strong understanding of Liberty formats including NLDM, CCS, ECSM, AOCV, POCV, and aging models.
- Experience characterizing multiple cell types, including combinational, sequential, clock gating, level shifters, retention, or power management cells.
- Knowledge of SPICE simulation, timing analysis, correlation methods, and scripting with Python, Tcl, or Perl.
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