Physical ASIC Design Implementation Engineer

Role overview

Physical implementation duties

• Set up implementation flows for the relevant library set and foundry node; configure low-power design using UPF.
• Perform floorplanning, power-grid design, timing-driven placement, static timing analysis, setup optimization, and clock tree synthesis.
• Restitch scan chains; perform timing-driven routing, including signal-integrity considerations, and in-place optimization across timing corners.
• Resolve setup and hold violations; perform signoff extraction, timing, and power analysis.
• Perform physical verification including DRC, ERC, LVS, and antenna checks, plus logic-equivalence checks.
• Collaborate through chip design and tapeout signoff, and look for AI methods to accelerate the design flow.

Candidate requirements

• Master’s degree in Electronics.
• Experience in hierarchical physical implementation in advanced nodes using either Synopsys or Cadence EDA tools.
• Experience with power-reduction techniques including gated clocks, voltage domains, memory retention, and switched-off power domains.
• Experience debugging tool, flow, or design issues.
• Excellent communication skills; English is required, and the candidate must be able to work in an international team.
• Leading partitioning and splitting top-level SDC constraints into timing budgets for sub-blocks is an asset.

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