Engineer

Role overview

About imec Qatar

DFT engineering work

• Architect DFT solutions for SoCs with multiple partitions and complex IP requirements; coordinate and negotiate DFT requirements.
• Implement and validate DFT techniques on SoCs and subsystems and define timing constraints for DFT test modes.
• Insert boundary scan, compression, MBIST/repair, and on-chip clock controllers in large low-power designs at advanced nodes, including 5nm and beyond.
• Generate test patterns, improve fault coverage, support post-silicon pattern debug, and diagnose memory and scan issues.
• Work with physical design teams on timing, signal and power integrity, and routing congestion; work with test engineering on silicon characterization and validation.
• Adopt AI methodology to speed up work.

Required experience and technical knowledge

• 5+ years of DFT insertion and ATPG experience; basic Verilog/VHDL fluency for test logic.
• Subsystem DFT ownership covering insertion and verification; complex PHY DFT integration such as PCIe, UCIe, or LPDDR5.
• Hands-on SDC constraint definition and DFT structure insertion and verification, including boundary scan, compression, MBIST/repair, OPCG/OCC, and ATPG.
• Experience with fault-coverage improvement and test debug for large low-power designs at 5nm and beyond.
• Expert knowledge of IEEE 1149.1, 1149.6, and 1687 (IJTAG), including ICL and PDL formats.
• Experience with Tessent, Genus/Modus, simulation tools, and scripting, especially TCL.

Preferred and advantageous experience

• Previous experience defining or maintaining DFT flows is preferred.
• Experience with Tessent SSN is a plus.
• Experience with IEEE 1838 and DFT for 2.5D/3D chiplets is a plus.

Work environment

• The posting describes a new Doha office, a multicultural and informal environment, and room for initiative and professional development.