Physical ASIC Design Implementation Engineer

Role overview

What you will do

• Set up implementation flows for the target libraries and foundry node, including low-power design with UPF.
• Perform floorplanning, power-grid design, timing-driven placement, clock-tree synthesis, and scan-chain restitching.
• Route with timing and signal-integrity considerations; optimize timing and resolve setup and hold violations.
• Complete signoff extraction, timing and power analysis, physical verification, and logic-equivalence checks.
• Collaborate with physical designers on signoff closure for tape-out.
• Consider AI methodologies to accelerate design-flow work.
• Leading partitioning and splitting top-level SDC constraints into sub-block timing budgets for hierarchical design is an asset.

Who you are

• Master’s degree in Electronics.
• Experience in hierarchical physical implementation in advanced nodes with either Synopsys or Cadence EDA tools.
• Experience with power reduction, including gated clocks, voltage domains, memory retention, and switched-off power domains.
• Experience debugging tool, flow, or design issues.
• Excellent communication skills; English is required, and you can work in an international team.

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