ASIC Digital Design , Staff Engineer
Role Overview
Synopsys develops silicon design, IP, simulation, analysis, and design services for AI-powered products.
The role focuses on building DesignWare IP cores for automotive, enterprise, consumer, and commercial applications.
The position works with high-speed digital logic, real silicon constraints, area and power budgets, and clock speeds above 600MHz.
Key Skills for This Role
Full Job Posting
Role overview
Synopsys develops silicon design, IP, simulation, analysis, and design services for AI-powered products.
The role focuses on building DesignWare IP cores for automotive, enterprise, consumer, and commercial applications.
The position works with high-speed digital logic, real silicon constraints, area and power budgets, and clock speeds above 600MHz.
What you'll be doing
- Architect and implement RTL designs for DesignWare IP cores and translate protocol specifications into micro-architectures and design documentation.
- Write synthesizable Verilog and SystemVerilog for data-path and control features such as Reed Solomon FEC, BCH, CRC, and MAC SEC.
- Drive synthesis, static timing, CDC, lint, and P&R-aware synthesis using tools such as Fusion Compiler.
- Collaborate with global engineering teams and customers to refine specifications and resolve design ambiguities.
- Lead technical reviews, debug complex RTL issues, and develop test strategies for quality and coverage.
- Mentor and technically lead RTL designers on coding practices, design trade-offs, timing closure, and process improvements.
- Use Perforce for version control and Perl or Shell scripting to automate design-flow tasks.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related technical field.
- At least 4 years of hands-on industry experience in ASIC RTL design.
Expected impact
Deliver robust, synthesizable IP for Ethernet, DDR, PCIe, USB, and other high-speed protocols.
Improve integration risk and time to market by delivering IP that meets area, power, performance, and timing targets.
Elevate team capability through mentorship and influence future IP architecture and product priorities.
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