ASIC Digital Design, Staff Engineer
Role Overview
Synopsys develops chip design, verification, IP integration, and software technologies for high-performance silicon and connected systems.
The Staff ASIC Digital Design Engineer will own a PCIe subsystem end to end, from architecture and micro-architecture through production RTL, reviews, and debug.
The role involves complex high-speed interface IP, clocking, resets, flow control, low power, and maintainable parameterized RTL.
Key Skills for This Role
Full Job Posting
Role overview
Synopsys develops chip design, verification, IP integration, and software technologies for high-performance silicon and connected systems.
The Staff ASIC Digital Design Engineer will own a PCIe subsystem end to end, from architecture and micro-architecture through production RTL, reviews, and debug.
The role involves complex high-speed interface IP, clocking, resets, flow control, low power, and maintainable parameterized RTL.
What you'll be doing
- Own RTL and micro-architecture for PCIe controller subsystems or major features from block level through subsystem integration.
- Write design specifications, implement production RTL, and drive the area through verification, synthesis, timing closure support, and design convergence.
- Resolve complex design and debug issues and escalate architecture trade-offs with clear options.
- Participate in and lead design reviews while enforcing coding standards, CDC/RDC, and code quality.
- Collaborate with verification, formal, emulation, and physical design to close bugs and integration issues.
- Support post-silicon and customer debug for the owned area.
- Mentor senior and junior engineers through reviews and guidance.
- Communicate subsystem status, risks, and dependencies.
What you'll need
- BSEE with 8+ years of relevant experience, or MSEE with 6+ years of relevant experience.
- Proven ownership of complex ASIC RTL from specification through tapeout or IP release.
- Strong PCIe digital design experience or equivalent high-speed protocol experience in CXL, AMBA, DDR, UCIe, Ethernet MAC, or similar.
- Experience with synthesizable RTL, clocking, CDC/RDC, resets, low power, and DFT awareness.
- Ability to define micro-architecture for an owned area and work from architecture specifications.
- Parameterized or configurable IP experience is a strong plus.
- Python, TCL, or Perl scripting is desirable, and AI-assisted design tools are a plus.
Working style
The role calls for a subsystem owner who is hands-on in RTL, precise in reviews, collaborative with design verification and physical design, and focused on closing issues.
The engineer will contribute to silicon-proven PCIe IP for commercial, enterprise, and automotive customers.
Apply for this job in 1 click
Skip the repetitive application forms
Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.
Trusted by over 500,000 job seekers on Base Career
More from this employer
More jobs at Synopsys
Product Management , Staff
Vancouver, CAN
Synopsys is seeking a product manager for its photonics design and simulation software portfolio, including OptoCompiler and Lumerical. The role owns product strategy, customer discovery, roadmap prioritization, launches
R&D Engineering, Sr Engineer
, IND
Synopsys seeks a Senior Engineer to build production-grade agentic AI applications for semiconductor engineering workflows. Candidates need 2+ years of production software experience, Python proficiency, and hands-on exp
Hardware Validation Senior Engineering Manager
Mississauga, CAN
Synopsys is seeking an experienced engineering manager to lead hardware development for silicon validation. The role covers high-speed PCB design, simulation, lab debugging, and team development; candidates need extensiv
Validation / Verification Eng, Manager - 18754
Nepean, CAN
Synopsys seeks a hands-on manager to lead silicon validation of memory interface IP in its Nepean lab. The role combines first-silicon bring-up, electrical characterization, debug, test automation, and team management. C
Layout Design, Staff Engineer
, IND
Synopsys is seeking an experienced custom memory layout engineer to own SRAM, Register File, ROM, and memory compiler IP layouts through signoff. Candidates need substantial custom memory layout experience, strong physic
Staff Digital Verification Engineer
, IND
Synopsys seeks an experienced digital verification engineer to lead verification of DesignWare IP, including PHY blocks and interface logic. The role requires 4+ years of hands-on verification experience, SystemVerilog/U
R&D Engineering, Sr Engineer
, IND
Synopsys is seeking a senior engineer to characterize and model standard cell libraries for advanced technology nodes. The role requires hands-on library characterization and Liberty modeling experience, alongside knowle
Senior Staff Analog Layout Engineer
, IND
Synopsys is seeking a senior analog layout engineer to design and deliver custom UCIe PHY layouts for chiplet products. The role focuses on advanced packaging, high-speed routing, physical verification, and cross-functio
Product Management , Staff
Vancouver, CAN
R&D Engineering, Sr Engineer
, IND
Hardware Validation Senior Engineering Manager
Mississauga, CAN
Validation / Verification Eng, Manager - 18754
Nepean, CAN
Layout Design, Staff Engineer
, IND
Staff Digital Verification Engineer
, IND
R&D Engineering, Sr Engineer
, IND
Senior Staff Analog Layout Engineer
, IND