ASIC Digital Design, Sr Staff Engineer

About Synopsys

Role Overview

What You Will Do

• Own verification for major IP blocks, subsystems, or cross-IP methodologies through final signoff and customer delivery.
• Define verification strategy, architecture, planning, and signoff criteria for complex IP projects, including Ethernet, USB, and similar protocols.
• Lead technical execution by setting objectives, tracking milestones, managing risk, and driving coverage and quality closure.
• Apply AI-assisted methods to debug, regression analytics, test generation, and coverage closure.
• Build reusable verification infrastructure, UVM environments, and scalable methodology improvements.
• Mentor engineers on test planning, debug, coverage analysis, and verification best practices.
• Collaborate with design, architecture, firmware, and quality teams to align verification deliverables with project goals.

Expected Impact

• Deliver thoroughly verified, customer-ready DesignWare IP that reduces integration risk and increases confidence for silicon teams.
• Improve verification efficiency through faster coverage closure, shorter regression cycles, reduced debug time, and fewer escaped defects.
• Advance reusable infrastructure and methodologies that improve execution quality and delivery predictability.
• Strengthen verification capability through mentoring and scalable best practices.
• Reduce project risk by identifying verification gaps early and ensuring robust signoff criteria before release.

Requirements

• BS or BE in Electrical or Electronics Engineering with 8+ years of IP or SoC verification experience, or MS with 6+ years.
• Demonstrated ownership of verification for complex IP blocks, subsystems, or cross-project methodologies with measurable quality results.
• Ability to lead verification teams and projects through technical influence and collaboration.
• Deep hands-on expertise in UVM, VMM, or OVM at unit and system levels.
• Strong proficiency in SystemVerilog, VCS or similar simulators, and associated debug tools.
• Practical experience applying AI-assisted methods to verification activities.
• Experience with DesignWare IP or similar synthesizable IP verification and familiarity with protocols such as Ethernet or USB.