Applications Engineering, Sr Staff Engineer

Senior Staff Verification Engineer

Sr Staff Applications Engineer, Simulation & Debug

Principal Application Engineer, VCS/Verdi

Senior Staff FAE, Verification Solutions

Sr Staff Technical Solutions Engineer, EDA

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years in verification, the kind where a missed edge case costs six months and millions of dollars, and you have learned to think like both the designer who built it and the engineer trying to break it. You know that simulation is not just about running tests, it is about understanding why a testbench stalls at 3am, why coverage is stuck at 87%, and what it takes to get a customer from "this doesn't work" to "this is faster than anything we've run before."

You are comfortable sitting with a customer's verification team, digging into their UVM environment or gate-level timing flow, and walking out with a deployment plan that actually works in their environment, not just in a demo. You do not wait for perfect documentation. You read waveforms, trace through SystemVerilog, script your way around problems, and know when to pull in R&D versus solve it yourself.

Competitive benchmarks do not intimidate you. You have run them, you know where VCS wins, and you can explain it in terms that matter to the person signing the contract. You care about the craft. At Synopsys, you will work on verification technology that powers tape-outs across the industry, and the customers you support will remember your name.

Drive customer deployments of VCS and Verdi simulation and debug platforms, working directly with design and verification teams to integrate tools into their existing flows

Diagnose complex technical issues across UVM testbenches, gate-level simulations, low power flows, and timing-aware verification environments

Lead competitive engagements and benchmarking efforts, demonstrating VCS/Verdi performance, capacity, and debug advantages against rival tools

Collaborate with R&D and product teams to gather customer requirements, reproduce field issues, and influence the product roadmap based on real deployment feedback

Develop and optimize automation scripts in Perl, Python, TCL, Shell, and Make to improve customer productivity and streamline verification workflows

Interface across global teams including product validation, field applications, and customer engineering to propose solutions and drive product improvements

Support customers through technical escalations, providing expertise in SystemVerilog, SVA, UVM, low power (UPF), and gate-level simulation methodologies

Enable customers to close verification faster and reach first-pass silicon success by deploying simulation technology that scales to their toughest designs

Influence the VCS and Verdi product roadmap by surfacing real-world customer challenges and competitive gaps that R&D can act on

Win competitive deals by proving performance, capacity, and debug superiority in head-to-head benchmarks that matter to customer schedules

Accelerate adoption of advanced features like AI-driven productivity tools, formal integration, and next-gen debug capabilities across your customer base

Reduce time-to-resolution for critical customer issues, turning escalations into deployments and deployments into long-term partnerships

Strengthen Synopsys' position as the verification platform of choice by making customers successful in ways they can measure and defend internally

Build institutional knowledge across the global applications team by documenting solutions, sharing best practices, and mentoring peers on complex verification challenges

Bachelor's or Master's in Electronics Engineering or equivalent, with 5-12 years of hands-on experience in verification or application engineering

Deep expertise in simulation technologies, UVM, SystemVerilog Assertions (SVA), and verification methodologies applied to real designs

Strong command of HDL languages including Verilog, VHDL, and SystemVerilog, with solid understanding of digital design fundamentals

Proven experience with gate-level simulation, timing-aware verification, and low power flows using UPF

Advanced scripting ability in Perl, Python, TCL, Shell, and Make, with comfort working in UNIX/Linux environments

Experience with Synopsys Verdi or similar waveform debug tools is a strong plus, as is knowledge of DPI, C/C++, SystemC, or functional safety standards

Exposure to generative AI technologies or AI-driven EDA workflows is a plus

You can walk into a customer meeting, listen to a verification problem described in half-formed sentences, and walk out with a clear technical plan and next steps

You are the person your team pulls in when a customer issue is stuck, not because you know everything, but because you know how to find the answer and who to ask

You manage multiple customer engagements at once without dropping threads, and you do not need reminders to follow up or close the loop

You push back when a proposed solution does not fit the customer's actual environment, and you are comfortable saying "that won't work, here's what will"

Travel does not faze you, whether it is onsite customer visits, regional workshops, or working across time zones with global R&D and field teams

You stay current, not because it is required, but because you are genuinely curious about what is next in verification, AI tooling, and EDA technology

Your recruiter will share more about the team structure and mission during the interview process.