Engineer

Role overview

Responsibilities

• Architect DFT solutions for SoCs with multiple sub-blocks or partitions and complex soft and hard IPs.
• Coordinate and negotiate DFT requirements; implement and validate DFT techniques on SoCs and subsystems.
• Define timing constraints for DFT test modes.
• Insert boundary scan, compression, MBIST/repair, and on-chip clock controllers for large low-power designs at advanced nodes.
• Generate test patterns; debug and improve fault coverage; support post-silicon test-pattern debug and diagnose memory and scan issues.
• Collaborate with physical design teams on timing violations, signal and power integrity issues, and routing congestion.
• Collaborate with test engineering on silicon characterization and validation.
• Adopt AI methodology to accelerate work.

Requirements and experience

• 5+ years of experience with DFT insertion and ATPG.
• Basic Verilog/VHDL fluency for writing test logic when needed.
• Experience owning subsystem DFT, including insertion and verification of DFT structures.
• Experience integrating DFT for complex PHY blocks such as PCIe, UCIe, or LPDDR5.
• Hands-on experience with SDC constraints, boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault-coverage improvement, and test debug for large low-power designs at 5nm and beyond.
• Expert knowledge of IEEE 1149.1, 1149.6, and 1687 (IJTAG), including ICL and PDL file formats.
• Experience with EDA tools such as Tessent, Genus/Modus, and simulation tools; scripting experience, especially TCL.
• DFT flow definition or maintenance experience is preferred; Tessent SSN experience is a plus.
• IEEE 1838 and DFT for chiplets (2.5D/3D) experience is a plus.

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