Verification Engineer, Senior

Role and team

Minimum qualifications

• Bachelor's degree in Science, Engineering, or a related field plus 2 or more years of ASIC design, verification, validation, integration, or related experience; alternatively, a relevant master's plus 1 or more year of experience, or a relevant PhD.

What you'll do

• Review digital design specifications and devise verification plans; develop SystemVerilog and UVM testbenches and test cases.
• Debug and bring up simulations; integrate analog behavioral models to validate mixed-signal design interactions.
• Collaborate across Design, Systems, Firmware, and Analog teams to resolve issues and achieve verification closure.
• Facilitate bit-matching between RTL designs and MATLAB system models; integrate third-party VIPs for Ethernet and PCIe compliance testing.
• Support post-silicon chip bring-up and develop automation and improvements to verification methodologies, processes, and infrastructure.
• Take opportunities to lead, plan, and coordinate tasks with teammates.

Technical qualifications

• SystemVerilog and UVM proficiency, including verification environments and testbenches, and experience with constrained-random verification and functional coverage.
• SerDes PHY, DSP, or analog mixed-signal verification experience is preferred but not required.
• Ethernet and PCIe knowledge is desirable; formal verification, gate-level simulation, and power-aware UPF verification exposure is noted.
• Listed tools and languages include SystemVerilog, UVM, Python, Perl, C/C++, and GNU Make.

About you

• Strong written and verbal communication; detail-oriented, organized, and able to manage multiple tasks.
• Self-motivated problem solver who takes project ownership, learns quickly, adapts to evolving technologies, and collaborates with peers.