Sr DFT Engineer

BS/MS/PhD in EE/ECE

At least 3+ years of industry experience

Understanding of Design for Test methodologies and DFT experience (e.g. JTAG 1149.x, IEEE 1500, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST)

Experience with SoC Level DFT Integration, Verification and RTL design for DFT

Experience with DFT strategies like Scan insertion, TPI, SSN, Hierarchical DFT and ATPG

Pre-Silicon test planning & verification strategy

Knowledge & experience of low power concepts, clock gating, power gating is a plus

Adept at root cause analysis and resolving DFT implementation issues

Must have good communication skills and the ability to work in a worldwide team environment

A past experience of working on an AI processor design is a huge plus

Experience working at startups

Knowledge of Low power DFT solutions

Experience of working with STA team to define DFT timing constraints

Working with ATE (Automatic Test Equipment) for bring-up, debugging, and yield improvement

Proficiency in Synopsys (TetraMAX/DFT Compiler) or Siemens/Mentor (Tessent) tools, Verilog/SystemVerilog

Good script skills including Perl, Tcl, Python, etc.

Knowledge of chiplet-based design limitations and their impact on physical design.

Experience in Sub-10nm designs

Familiarity and hands-on experience with Cadence toolsets.