Senior Design Verification Engineer

Responsibilities

• Hands-on system-level and block-level verification.
• Development of test plans and coverage plans.
• Testbench development and execution using UVM or other advanced DV methodologies.
• Creation of verification infrastructure and flows.
• Leverage architecture models and emulation environments to help verify large AI network functionality on the design.
• Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers.

Requirements

• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of industry experience developing verification testbenches.
• Knowledge of verification methodologies (UVM or similar).
• Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects.
• Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems.
• Understanding of Verilog, SystemVerilog, and UVM.
• Proven track record of first-pass silicon success.
• Strong communication skills, both written and spoken.

Preferred Qualifications