Sr. ASIC Layout Design Engineer

What You Bring:

• Bachelor’s degree in engineering or related field with 10+ years of industry experience
• Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes
• Proficiency in Cadence Virtuoso XL for connectivity-aware design
• Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques
• Experience with custom cell-based layout and top-level floor planning, with work on focal-plane arrays a plus
• Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects
• Excellent communication skills and the ability to work effectively within a multidisciplinary team
• Programming/scripting skills in SKILL, TCL, Shell, or Python
• Salary Range:
• The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position.
• Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.
• Teledyne is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws.