SMTS Layout Design

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Layout Designers to join our Bufferchip team in Bangalore.

Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

As a Lead Layout Design Engineer, the candidate will be working with IDC and other locations as needed.

He will be responsible for the layout design and coordination of layout execution across different location.

Mostly working on planar technology with high current blocks and high drive ICs

• Demonstrate leadership skill in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment.
• Mentor and provide technical guidance to team members in their execution of layouts and review their work to meet quality and the schedule.
• Participate in technical discussions and represent layout team in all the discussions with internal customers.
• Contribute to layout procedures and methodology improvements.

• Typically requires more than 9+ years of experience in analog/mixed-signal layout design of deep sub-micron CMOS/FinFET circuits.
• Solid understanding of layouts with process nodes ranging from 40nm, 28nm, 22nm and FINFET is must.
• Expertise in layout techniques for managing cross talk, high speed signals, minimizing parasitic, IR drop, EM, RC delays and high-power routing.
• Understanding the layout requirement for ESD(HBM/clamps), EOS and latch up technique is must.
• Understanding of Analog Layout techniques for LOD/STI, WPE, PSE, OSE concept is must.
• Should be involved in finalizing the bump out/floorplan in discussing with package engineer and cross function teams.
• Should be involved in multiple TO’s and post TO producer understanding.
• Expertise in Cadence XL/VXL and Mentor Graphic Calibre DRC/LVS/Antenna Star-RCXT is must.
• Scripting skills for layout automation is a plus.