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Senior Embedded SW/Firmware Design Engineer

CHAOS Industries
El Segundo, USA
Senior · 5+ years experience
Onsite
Discovered 4 days ago

Full Job Posting

Responsibilities:

  • Design and implement complex FPGA designs targeting our next-generation sensor products
  • Support system integration of FPGA designs with complex software systems
  • Support deployed FPGA capabilities in the hands of our U.S. and international customers
  • Work full-time on-site in our office in Hawthorne, California
  • Minimum Requirements:
  • Bachelor’s or higher degree in Computer Engineering, Electrical Engineering, Computer Science or related degree
  • 5+ years of experience in a professional setting performing detailed digital RTL design targeting FPGAs
  • Extensive experience with the entire FPGA design life cycle: RTL design, behavioral simulation, place and route, timing analysis, hardware integration
  • Extensive experience developing in Verilog and SystemVerilog
  • Extensive experience with the ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream)
  • Extensive experience with the AMD (Xilinx) Vivado Design Suite and SoC FPGAs (Zynq, Ultrascale/Ultrascale+, Versal)
  • Experience with Network Protocols (TCP/UDP/IP)
  • Experience with Serial Protocols (I2C, JTAG, UART, SPI, CAN)
  • Experience using Bash and Python for scripting and testing
  • Experience modifying software drivers and applications when needed to validate FPGA designs
  • Experience with Agile lifecycle processes including Scrum, Continuous Integration, and Test-Driven Development Methodologies
  • Ability to work with minimal supervision and collaborate on small teams
  • U.S. Person status is required as this position will require the ability to access U.S.-only data systems
  • Preferred Requirements:
  • Experience designing and implementing highly performant baseband signal processing in an FPGA
  • Experience translating high level algorithms from Simulink/MATLAB or similar into RTL including FPGA Vendor IP implementations
  • Experience developing and implementing software drivers (C/C++/Python) to interface with FPGA designs
  • Experience with FPGA Ethernet IP blocks (1G/10G/40G/100G)
  • Experience with Software-Defined Radios (SDRs) (e.g. Ettus, NI, HackRF)
  • Experience with Analog Device Transceivers
  • Experience in Ground or Airborne Sensors (Radars, EO/IR, EW, etc.)
  • Experience with Time Synchronization technologies (NTP / PTP)
  • Experience with HLS Synthesis and languages (C/C++/SystemC/Chisel)
  • Experience with VHDL
  • Experience with high-speed, multi-layer, digital printed circuit board (PCB) design
  • Current or previous DoD security clearance
  • Experience with GPUs and/or AI engines
  • Experience with git
  • Experience with Bitbucket CI, Jenkins or similar CI/CD flows
  • Experience with DoD & related System/SW Architectures and messaging standards (e.g. OMS, SOSA, Link-16, etc)
  • Why CHAOS?
  • Health Benefits: Medical, dental, and vision benefits 100% paid for by the company
  • Additional benefits: 401k (+ 50% company match up to 6% of pay), FSA, HSA, life insurance, and more
  • Our Perks: Free daily lunch, ‘No meeting Fridays’, unlimited PTO, casual dress code
  • Compensation Components: Competitive base salaries, generous pre-IPO stock option grants, relocation assistance, and (coming soon!) annual bonuses
  • Team Growth: 500 employees and counting across 5 global offices
  • Salary range: $160,000 - $290,000
  • The stated compensation range reflects only the targeted base compensation range and excludes additional earnings such as bonus, equity, and benefits. If your compensation requirements fall outside of the range, we still encourage you to apply. The salary range for this role is an estimate based on a range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations.
  • #LI-onsite

Qualifications

  • Experience with Network Protocols (TCP/UDP/IP)
  • Experience with Serial Protocols (I2C, JTAG, UART, SPI, CAN)
  • Experience with Agile lifecycle processes including Scrum, Continuous Integration, and Test-Driven Development Methodologies
  • Experience with FPGA Ethernet IP blocks (1G/10G/40G/100G)
  • Experience with Software-Defined Radios (SDRs) (e.g. Ettus, NI, HackRF)
  • Experience with Analog Device Transceivers
  • Experience with Time Synchronization technologies (NTP / PTP)
  • Experience with HLS Synthesis and languages (C/C++/SystemC/Chisel)
  • Experience with VHDL
  • Experience with high-speed, multi-layer, digital printed circuit board (PCB) design
  • Experience with GPUs and/or AI engines
  • Experience with git
  • Experience with Bitbucket CI, Jenkins or similar CI/CD flows
  • Experience with DoD & related System/SW Architectures and messaging standards (e.g. OMS, SOSA, Link-16, etc)

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