Infra Design Verification Sr Engineer

Role overview

Minimum qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field plus 2+ years of hardware engineering or related work experience; or a relevant master's degree plus 1+ year; or a relevant PhD.
• Strong proficiency in SystemVerilog, UVM, and verification methodologies.
• Deep understanding of PCIe generations 3–6, CXL 1.1/2.0/3.0, AXI/CHI, and SMMU/Coresight architecture.
• Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA; expertise in SVA and coverage-driven testing.
• Proficiency in Perl, Python, or Tcl scripting; knowledge of UPF, formal verification, and performance/power optimization.
• Experience with coverage-driven verification and constraint-random testing.

Key responsibilities

• Develop and maintain UVM verification environments and plans for PCIe, CXL, AXI, and CHI.
• Perform block- and top-level verification, coverage analysis, assertion-based verification, and regression testing.
• Collaborate with RTL, architecture, and validation teams to derive verification strategies and close coverage.
• Use third-party VIPs and build or enhance scoreboards, agents, monitors, and sequences.
• Integrate and validate SMMU and Coresight in subsystem environments; debug RTL and gate-level simulation failures.
• Drive verification closure and consider performance, power, and cost optimization.
• Mentor junior engineers and improve verification methodology.

Preferred qualifications

• Bachelor’s, master’s, or Ph.D. in Electrical, Electronics, or Computer Engineering.
• 3+ years of ASIC/subsystem/SoC verification experience.
• Peripheral protocol experience such as PCIe, USB, or Ethernet is a plus.
• Post-silicon validation and lab bring-up exposure is desirable.

Company context