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Verification Engineer
Luxoft
Hyderabad, IND
Full-time
Junior · 2–4 years experience
Onsite
Discovered 2 weeks ago
Xilinx Vivado, specifically the implementation flow FPGA design flow static timing analysis and design constraints digital / logic design debug skills 2-4 years of experience Experience: Minimum 2, maximum 4 years.
Key Skills for This Role
Xilinx Vivado, specifically the implementation flow FPGA design flow static timing analysis and design constraints digital / logic design debug skills 2-4 years of experience Experience: Minimum 2, maximum 4 years.
Full Job Posting
Responsibilities
- Tests the Xilinx Vivado FPGA implementation flow itself - placer, routing, static timing analysis - and analyses quality of results. EDA tool QA for an FPGA engineer, not ASIC verification.
SKILLS
- Must have
- Xilinx Vivado, specifically the implementation flow * FPGA design flow * static timing analysis and design constraints * digital / logic design * debug skills * 2-4 years of experience * Experience: Minimum 2, maximum 4 years.
Nice to have
- EDA company experience * scripting / automation (Tcl, Python) * AI tool usage
Qualifications
- Must have
- Xilinx Vivado, specifically the implementation flow * FPGA design flow * static timing analysis and design constraints * digital / logic design * debug skills * 2-4 years of experience * Experience: Minimum 2, maximum 4 years.
About Luxoft
Technology10,001+Founded 2000
Global IT services and consulting company
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