TPU RTL Design Engineer, Google Cloud

Responsibilities

• Work independently to create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.
• - Work independently to create and review clock control subsystem's design micro-architecture specifications. - Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines. - Work with architecture and power teams to evaluate features and their impact. - Work with Design Validation (DV) teams to create test plans to verify and debug design RTL. - Work with physical design teams to ensure design meets physical requirements and timing closure.

Minimum qualifications:

Preferred qualifications:

Qualifications

• Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. - Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL. - Experience using Python, Tcl, or Perl for automating design tasks and data analysis. - Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. - 5 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration. - Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization. - Knowledge of processor design or accelerators and of high-performance and low power design techniques. - Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion. - Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data.