Senior Verification Engineer

Role overview

Key responsibilities

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments, testbenches, assertions, scoreboards and coverage models.
• Run directed and constrained-random verification; analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration, automation, regression and CI workflows.
• Participate in design reviews and verification sign-off; mentor and support junior colleagues.

Required qualifications and skills

• Degree in electronic engineering, computer engineering or a related discipline.
• At least three years of digital ASIC and/or FPGA design verification experience.
• Strong SystemVerilog and UVM skills; understanding of RTL design and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency and scripting in Python, Tcl or Bash.
• Strong analytical, debugging and problem-solving skills, and experience using AI to accelerate verification without sacrificing quality.
• Ability to work across multiple teams.

Desirable experience

• Experience in 4G/5G, NTN, satellite communications or DSP systems is desirable.
• Knowledge of modem architectures and Layer 1 processing is desirable.
• Formal verification, FPGA prototyping, CI environments, and MATLAB or equivalent modelling tools are desirable.

Compensation and benefits

• Salary is competitive and depends on skills and experience.
• Annual bonus pays up to 20% of salary depending on performance; EMI share options are issued periodically.
• Benefits include pension and private health insurance.

Working arrangements

• The company offers hybrid working and flexible working hours.

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