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Senior Verification Engineer

AccelerComm
Bristol, GBR
Full-time
Mid · 3+ years experience
Hybrid
Discovered 2 weeks ago
SystemVerilogUVMPythonTclBashMATLAB

Full Job Posting

Key Responsibilities

  • Develop verification plans from design and architecture specifications.
  • Create and maintain SystemVerilog/UVM verification environments.
  • Develop testbenches, assertions, scoreboards and coverage models.
  • Execute directed and constrained-random verification.
  • Analyse coverage and debug RTL and verification issues.
  • Support subsystem and system-level integration activities.
  • Contribute to automation, regression and CI workflows.
  • Participate in design reviews and verification sign-off.
  • Mentor and support junior colleagues

Skills, Knowledge & Expertise

  • Required
  • Degree in Electronic Engineering, Computer Engineering or a related discipline.
  • At least 3 years experience verifying digital ASIC and/or FPGA designs.
  • Strong SystemVerilog and UVM skills.
  • Understanding of RTL design principles and hardware implementation.
  • Experience with coverage-driven and assertion-based verification.
  • Linux proficiency and scripting skills (Python, Tcl or Bash).
  • Strong analytical, debugging and problem-solving skills.
  • Experience using AI to accelerate verification without sacrificing quality
  • Ability to work across multiple teams
  • Desirable
  • Experience in 4G/5G, NTN, satellite communications or DSP systems.
  • Knowledge of modem architectures and Layer 1 processing.
  • Experience with Formal Verification, FPGA prototyping and CI environments.
  • Familiarity with MATLAB or equivalent modelling tools.

Job Benefits

  • We pay competitive salaries which depend on skills and experience. We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance. We operate flexible working hours and offer hybrid working.

Requirements

  • Required
  • Degree in Electronic Engineering, Computer Engineering or a related discipline.
  • At least 3 years experience verifying digital ASIC and/or FPGA designs.
  • Strong SystemVerilog and UVM skills.
  • Understanding of RTL design principles and hardware implementation.
  • Experience with coverage-driven and assertion-based verification.
  • Linux proficiency and scripting skills (Python, Tcl or Bash).
  • Strong analytical, debugging and problem-solving skills.
  • Experience using AI to accelerate verification without sacrificing quality
  • Ability to work across multiple teams
  • Desirable
  • Experience in 4G/5G, NTN, satellite communications or DSP systems.
  • Knowledge of modem architectures and Layer 1 processing.
  • Experience with Formal Verification, FPGA prototyping and CI environments.
  • Familiarity with MATLAB or equivalent modelling tools.

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