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Senior TPU Compute RTL Design Engineer

Google
Sunnyvale, USA
Senior · 8+ years experience
Onsite
USD 163000-236000 / year
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Responsibilities

  • Create and own microarchitecture for Compute accelerator IPs.
  • Develop implement, and maintain design blocks or components.
  • Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
  • Work with design verification and validation teams to create testplans to verify, and debug design RTL.
  • Work with physical design teams to ensure design meets physical requirements and timing closure.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with digital design using SystemVerilog RTL.
  • Experience with power, performance and area optimizations.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience interacting with software, architecture, physical design and other cross-functional teams.
  • Knowledge of processor design, accelerators, or memory hierarchies.

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