Senior Staff VLSI Design Engineer (SystemC, Functional Modeling, C++ , Verification)
Role Overview
Senior VLSI engineering role focused on functional modeling and verification for flash and advanced memory technologies.
Key Skills for This Role
Full Job Posting
Role Overview
Senior VLSI engineering role focused on functional modeling and verification for flash and advanced memory technologies.
Job Responsibilities
- Develop C++ and SystemC models and create tests.
- Debug issues in the firmware environment.
- Validate developed models using SystemC, SystemVerilog, and UVM testbenches.
- Debug failures and perform root-cause analysis with cross-functional teams.
- Mentor junior engineers.
Experience and Qualifications
- Requires 12+ years of relevant work experience.
- Requires hands-on C++ and SystemC model development and test creation experience.
- Requires prior C-based test or testbench development experience.
- Requires a bachelor's or master's degree in electronics and communication, embedded systems, or a related background.
- Requires strong problem-solving, communication, leadership, and mentoring skills.
Technical Skills
- Python coding is a plus.
- Knowledge of NAND concepts is an advantage.
- Memory and digital design knowledge, including SRAM, DRAM, ROM, and flash logic, is preferred.
- Verilog, SystemVerilog, and UVM are plus skills.
- Tools include Visual Studio, Git, and Bitbucket.
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