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Senior Staff CPU Cache Subsystem Design Engineer

Google
Austin, USA
Senior · 15+ years experience
Onsite
USD 240000-333000 / year
Discovered 1 weeks ago

Full Job Posting

Responsibilities

  • Lead a team of digital design engineers working on CPU functional units, focusing specifically on microarchitecture and RTL design for next-generation CPU subsystems.
  • Review and propose performance-enhancing microarchitecture features while collaborating closely with cross-functional software, architecture, and performance teams on trade-off studies.
  • Deliver comprehensive plans to achieve project milestones and execution goals, ensuring the production-quality design meets strict scheduling targets.
  • Collaborate directly with verification, physical design, and power analysis teams to ensure designs successfully meet frequency, power, and area targets.
  • Direct load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.

Minimum qualifications:

  • Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
  • Experience leading technical teams for modern processor subsystems with high speed, lower power design.
  • Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications:

  • Experience with ARM instruction set architecture.
  • Experience with mobile CPU subsystem.
  • Experience with mobile SOC architecture/integration.

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