Senior RTL Design Engineer, TPU Compute

Responsibilities

• Create and own microarchitecture for Compute accelerator IPs.
• Develop implement, and maintain design blocks or components.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design verification and validation teams to create testplans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.
• - Create and own microarchitecture for Compute accelerator IPs. - Develop implement, and maintain design blocks or components. - Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines. - Work with design verification and validation teams to create testplans to verify, and debug design RTL. - Work with physical design teams to ensure design meets physical requirements and timing closure.

Minimum qualifications:

Preferred qualifications:

Qualifications

• Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience with digital design using SystemVerilog RTL. - Experience with power, performance and area optimizations. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. - Experience interacting with software, architecture, physical design and other cross-functional teams. - Knowledge of processor design, accelerators, or memory hierarchies.