Senior Principal Design Verification Engineer

Position Overview

Key Responsibilities

• Architect mixed-signal verification environments with RNM and AMS model integration.
• Develop verification plans and strategies for automotive PMIC products.
• Set up GLS flows and correlate results with RTL simulations.
• Debug switched-mode regulators, LDO regulators, and mixed-signal interfaces.
• Analyze timing, power, and functional correctness across PVT corners.
• Collaborate with design, application engineering, ATE, and silicon validation teams.
• Mentor junior engineers and establish verification methodologies.
• Troubleshoot analog-digital interactions using simulation and measurement techniques.
• Improve verification tools, infrastructure, and methodologies, including AI-based solutions.
• Maintain verification documentation, test plans, and coverage.

Required Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of mixed-signal or analog circuit verification experience.
• Deep knowledge of mixed-signal verification environment architecture and implementation.
• Hands-on RNM and AMS model integration experience.
• Proficiency with RTL and behavioral simulation tools such as Spectre and Xcelium.
• Strong GLS flow setup and debugging experience.
• Expertise debugging analog blocks and digital RTL.
• Automotive PMIC or power management IC design and verification experience.
• Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
• Understanding of UVM, assertions, and coverage-driven verification.
• Experience across functional, post-silicon, and ATE test correlation domains.
• Leadership, mentoring, problem-solving, and analytical skills.

About Renesas