Senior Design Verification Engineer

Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies. Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams. Execute the test plan by adding testcases and tracking verification through coverage driven metrices. Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage. Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow. Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features. Handle occasional on-call responsibilities for addressing hardware issues reported by our customers. Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience Doctorate in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR equivalent experience 7+ years technical engineering experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals