Senior Analog Layout Engineer

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters. Ciena's WaveLogic portfolio powers optical fiber transmission solutions and contributes significantly to innovation in telecommunications. This opportunity enables leadership in the physical implementation of advanced high-speed analog circuits using BiCMOS technologies. The role focuses on delivering high-performance analog layout that supports next-generation broadband fiber-optic modem solutions. How you will make an impact:

• Lead block and macro-level layout development, including floor planning, layout creation, and optimization.
• Evaluate layout feasibility across multiple circuit topologies and collaborate with analog designers to determine implementation trade-offs.
• Execute physical verification and electromigration checks.
• Contribute to team success through collaboration, knowledge sharing, and participation in team activities.
• Mentor junior layout engineers involved in layout implementation activities. The must haves:
• Education: a minimum of Bachelor of Engineering, Science, Computer Science, or other applicable scientific discipline.
• Experience: Experience in a leading analog high-speed layout role in advanced BiCMOS and/or CMOS technologies with industrial experience.
• Ability to work independently and collaboratively within a team environment.
• Ability to address complex technical problems using a methodical approach.
• Excellent written and verbal English communication skills.
• Utilization of analog design tools from Cadence, Mentor, and Synopsys, including Virtuoso, Calibre PERC, PEX, etc.
• History of successful analog circuit product deliveries. The Nice to haves:
• Experience in deep-submicron CMOS
• Development of automation scripts and Pcells to improve layout design flows.
• Experience with digital synthesis and place and route Pay Range: The annual salary range for this position in Canada is $114,000 - $182,000 CAD Considerations for Germany will reflect local currency and ranges. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.