Physical Design Engineer Intern (Toronto)

Physical Design Engineer Intern (Toronto)

About Astera Labs

The role

What you’ll do

Basic qualifications

• Currently pursuing a bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Coursework, project, research, or hands-on experience with digital logic, VLSI, ASIC design, computer architecture, or semiconductor engineering.
• Foundational understanding of timing, setup and hold, clocks, power, placement, routing, or physical verification concepts.
• Familiarity with Unix/Linux command-line environments and at least one scripting or programming language, such as Tcl, Python, shell, or C/C++.
• Strong analytical and debugging skills, attention to detail, and interest in understanding how designs become manufacturable silicon.
• Strong written and verbal communication, organization, and time-management skills.
• A hands-on work ethic, curiosity, learning agility, and ability to take ownership of assigned deliverables.

Preferred qualifications

• Experience with synthesis, floorplanning, placement, clock-tree synthesis, routing, static timing analysis, or physical-verification tools.
• Familiarity with EDA tools such as Fusion or Genus, Innovus, PrimeTime, Calibre, Voltus, or equivalent tools.
• Understanding of PVT corners, OCV/AOCV/LVF, timing closure, congestion, power planning, EMIR, DRC, LVS, or antenna checks.
• Experience writing Tcl, Python, shell, or Make-based automation for design flows and report analysis.
• Familiarity with standard-cell libraries, LEF/DEF, Liberty files, SDC constraints, SPEF extraction, or PDK concepts.
• Interest in PPA optimization, reproducible flow infrastructure, and connectivity products used in AI, cloud, server, or networking systems.
• Equal opportunity
• Astera Labs is committed to an inclusive workplace and considers qualified applicants without regard to protected characteristics under applicable law.

Equal opportunity

Responsibilities

• Set up and run physical-design flow stages for a block using established methodologies and reproducible work areas.
• Review RTL and physical-design inputs, including netlists, constraints, technology files, libraries, and parasitic or extraction data.
• Support synthesis, floorplanning, power-grid planning, placement, clock-tree synthesis, routing, and implementation optimization.
• Analyze timing reports, slack, skew, transition, congestion, utilization, and other quality-of-results metrics.
• Help investigate setup and hold violations and evaluate fixes such as cell sizing, buffering, Vt swaps, useful skew, and routing optimization.
• Review physical-verification and power-integrity results, including DRC, LVS, antenna, electromigration, and IR-drop findings.
• Use Unix/Linux and Tcl or other scripting tools to automate runs, parse reports, compare experiments, and improve flow reproducibility.
• Debug tool errors, warnings, broken stages, and unexpected QoR changes by examining logs, configurations, and generated reports.
• Collaborate with front-end design, timing, EMIR, physical-verification, CAD, and other engineering teams across handoffs.
• Document experiments, assumptions, results, and recommendations for future implementation work.