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Principal Post-Silicon Validation Engineer

Astera Labs
San Jose, USA
Lead · 8–12 years experience
Onsite
Discovered 2 weeks ago
PythonCommunication

Full Job Posting

Key Responsibilities

  • Post-Silicon Validation Leadership
  • Architect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production release
  • Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams
  • Lead lab bring-up of new silicon, including board, firmware, and software readiness
  • Debug and Characterization
  • Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary
  • Characterize high-speed serial link performance, including margining, signal integrity, and compliance, across process, voltage, and temperature
  • Partner with design and DFT teams to feed findings back into current and future product generations
  • Automation and Infrastructure
  • Develop scalable validation automation frameworks and test content using Python and C/C++
  • Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughput
  • Analyze large validation datasets to identify trends, outliers, and risks early
  • Technical Leadership
  • Mentor engineers and set best practices for validation methodology across the team
  • Collaborate with customers and Field Applications Engineers to reproduce and resolve system-level issues

Basic Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
  • 8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization
  • Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer
  • Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies
  • Strong scripting and programming skills in Python and/or C/C++ for test automation
  • Proven ability to debug complex hardware and firmware issues to root cause

Preferred Qualifications

  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field
  • Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products
  • Experience with SerDes characterization, equalization tuning, and link margining
  • Track record of taking multiple products from first silicon to volume production
  • Strong cross-functional communication skills and the ability to lead without direct authority
  • Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
  • We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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