Lead Product Validation Engineer

Role overview

Responsibilities

• Use HDL-based simulation or emulation and EDA tools to debug design and verification problems.
• Automate processes using scripting.
• Design and implement complex functional verification environments for complex digital systems, including SoCs.
• Collaborate with customer peers, management, and teams across functions and geographies.

Qualifications

• Electrical, electronics, or computer science engineering background.
• Very good understanding of Verilog and/or VHDL and experience using them in simulation or emulation.
• Working knowledge of EDA tools and experience debugging design or verification problems.
• Experience in scripting for process automation and in SystemVerilog, C++, and UVM.
• Experience verifying complex digital systems and designing and implementing functional verification environments.
• B.Tech, M.Tech, B.E., or M.E. with 3–6 years of relevant experience.
• Strong written, verbal, and presentation skills; ability to collaborate across functions and geographies.
• Knowledge of PCIe, USB 3/4, or DisplayPort is an added advantage.

About Cadence