Lead Hardware Engineer - DFT IP R&D

Position Overview

Job Responsibilities

• Develop design-for-testability tools and DFT IP features for the MODUS product.
• Design and verify Verilog, SystemVerilog, and UVM RTL and test benches.
• Work on full scan, compressed and uncompressed scan, memory BIST, JTAG, IEEE 1500, and boundary scan at block and SoC levels.
• Provide R&D support through problem analysis, debugging, and feature development.
• Optimize synthesis results for timing, area, and power.
• Contribute to research and innovative EDA solutions.
• Design, develop, troubleshoot, debug, and support the MODUS software product.
• Improve usability and quality through feature enhancement and rigorous verification.

Job Qualifications

• Proficient in RTL design using Verilog and SystemVerilog.
• In-depth knowledge of front-end EDA tools, including simulators, linters, and CDC checkers.
• Experience with SystemVerilog assertions, checkers, and advanced verification techniques.
• Knowledge of Perl or Python scripting is highly desirable.
• Knowledge of DFT methodologies is a plus.
• Strong foundational knowledge of data structures and algorithms.
• Familiarity with synthesis and static timing analysis.
• Excellent written and verbal communication and presentation skills.
• Experience with EDA tool development concepts is a plus.

Position Qualifications

• M.Tech, M.E, B.Tech, B.E. in EE, ECE, CS, or equivalent.
• Good understanding of digital electronics.
• Prior knowledge of Verilog, SystemVerilog, and EDA tools is required.