Jr. Product Engineer

Role overview

NPI and cross-functional support

• Support NPI from concept through product release and transfer to full-volume manufacturing.
• Collaborate with project, design, marketing, validation, test, characterization, quality, reliability, applications, and operations teams.
• Track backend NPI progress, timelines, milestones, and program logistics; support milestone reviews.
• Prepare production release deliverables and OSAT manufacturing documentation.

Test, characterization, and yield

• Support DfT and DfM requirements, ATE test program development and optimization, product characterization, correlation, and release.
• Help prepare datasheet specifications and production test limits; develop wafer-level and bench characterization plans.
• Analyze ATE and bench results across process, voltage, and temperature variations; support yield modeling, DOE, yield analysis, and test optimization.
• Support validation and reliability qualification and identify opportunities to reduce yield loss.

Manufacturing quality and improvement

• Monitor yield and quality metrics and support review of test coverage, test limits, and guard banding.
• Assist with failure analysis, root cause investigation, and corrective and preventive actions for field returns and RMA cases.
• Work with foundry process and packaging teams to resolve issues during fabrication, packaging, die sort, and final package testing.
• Contribute to lifecycle monitoring, cost reduction, and continuous improvement.

Minimum qualifications

• Bachelor’s degree in Electrical Engineering or a related field; a master’s degree is a plus.
• At least two years of semiconductor product, test, or design engineering experience; relevant internship or co-op experience is considered.
• Basic familiarity with statistical theory and data analysis tools such as Excel or JMP.
• Foundational knowledge of semiconductor physics and analog/mixed-signal IC design principles.
• Strong analytical, problem-solving, and communication skills, and eagerness to learn.

Preferred exposure

• Exposure to or coursework in DFM, DFT, and ATE test methods is a plus.
• Familiarity with Advantest or Teradyne high-speed digital ATE platforms or bench test equipment is a plus.
• Basic awareness of JEDEC, HTOL, ESD, latch-up, and semiconductor reliability qualification is a plus.

Pay

• The estimated pay range is CAD $75,000–$84,000; the posting does not specify the pay period.