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Early Career - GPU Top Level Physical Design Engineer

Apple
Cambridge, GBR
Full-time
Entry
Onsite
Discovered 2 weeks ago
ASICFloorplanningP&R

Full Job Posting

Description

As a GPU Top Level Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the physical design team, as you develop methodologies and “best known methods” that will enable best-in-class GPU design. You will develop PD guidelines and checklists, drive execution, and supervise progress. Be the focal point for place and route integration at the top level. You will need to communicate and drive the needs of PD with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Minimum Qualifications

  • Minimum of BSc/MSc in EE and some relevant experience.
  • Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.

Preferred Qualifications

  • Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
  • Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
  • Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.
  • Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
  • Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs.
  • Understanding of GPU architecture and design units.
  • Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
  • Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows.

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