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Design Verification Engineer, Silicon Engineering
Google
Bengaluru, IND
Mid · 4+ years experience
Onsite
Discovered 2 weeks ago
Full Job Posting
Responsibilities
- Create and improve constrained-random verification environments using SystemVerilog and UVM. Use SystemVerilog Assertions (SVA) and formal tools for formal verification.
- Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement power-aware test cases, including stress and corner-case scenarios, for robust power integrity.
- Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
- Plan the verification of complex digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience verifying digital logic at RTL using System Verilog for FPGAs and ASICs.
- Experience with UVM Testbenches/environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Expertise in creating/using verification components and environments in UVM methodology at IP or Subsystem level.
- Experience with image processing, computer vision or machine learning IPs.
- Experience with AMBA(APB/AXI/ACE) or other standard protocols.
- Familiarity with CPU, GPU or other compute/ML architectures.
- Excellent communication and collaboration skills with the ability to work with cross-functional teams.
About Google
Technology10,001+Founded 1998
Technology company specializing in search, advertising, cloud computing, and AI
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