Design Verification Engineer

Key responsibilities

• Create and maintain verification test plans based on design specifications.
• Develop UVM-based directed and constrained-random tests, debug simulation failures, and quickly identify design, testbench, or test issues.
• Define functional coverage models and perform coverage analysis and closure.
• Create and maintain SystemVerilog Assertions (SVA) for 3D NAND designs based on verification requirements.
• Develop, maintain, and enhance the UVM-based verification environment to support evolving design and verification requirements.
• Develop and maintain mixed-signal full-chip models and verification environments, including analog behavioral models, cell-level testbenches, and full-chip mixed-signal netlists and testbenches.
• Develop scripts and tools to automate verification workflows, regression execution, results processing, and data collection.
• Master’s degree with 3+ years of relevant experience, or bachelor’s degree with 5+ years, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Prior experience in pre-silicon verification of memory products is required.
• Hands-on experience with UVM, SystemVerilog Assertions, and formal property verification.
• Hands-on experience with mixed-signal verification, modeling, and simulation, supported by strong knowledge of digital and analog circuit design.
• Strong data analysis capabilities, with the ability to communicate technical findings clearly through written reports and presentations.
• Strong independent debugging and problem-solving skills, with proficiency in programming or scripting for design and verification automation.
• Excellent written and verbal communication skills, with the ability to collaborate effectively across design, verification, modeling, and cross-functional teams.
• Preferred qualifications include memory-industry verification experience, full-chip and regression verification, code and functional coverage closure, Python, Perl, or shell scripting, AI-assisted workflows, and commercial simulation, formal, and mixed-signal tools.
• This position is also eligible to participate in Solidigm's restricted stock unit (RSU), restricted cash unit (RCU), and cash bonus programs. In addition, Solidigm offers a benefits package that includes medical, dental, vision, supplemental life and AD&D insurance; short- and long-term disability; healthcare and dependent care flexible spending accounts, and a company match on eligible 401(k) plan contributions.
• The compensation range for this role is $121,280- $194,100. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

This is a Hybrid role reporting out of Rancho Cordova, California 3 days per week.