Staff VLSI Design Engineer (CAD)

Company

Role Overview

Responsibilities

• Develop layout automation and utilities in Cadence SKILL and SKILL++.
• Develop and validate physical verification tools and flows for parasitic extraction, EMIR drop, and substrate noise analysis.
• Test and validate tools, evaluate new methods, and develop quality-improvement procedures.
• Automate deck and technology-file generation and validation.
• Create layout test structures, validate verification rules, and troubleshoot errors in Cadence Virtuoso.
• Develop agentic AI flows for automated execution, bottleneck detection, violation triage, and closure decisions.

Technical Skills

• Use Cadence Virtuoso and Analog Design Environment tools such as FineSim or PrimeSim.
• Work with Calibre SVRF and ICV LVS decks and integrate physical verification flows.
• Use SKILL, Python, Unix, Perl, or Tcl scripting, with proficiency in one or more listed languages.
• Use revision control software such as Git, Perforce, or Synchronicity.
• StarRC experience is a plus.

Qualifications

• Hold a master’s degree in Electronics, Electrical Engineering, or a comparable subject.
• Have at least 7 years of mixed-signal CAD design-flow development experience.
• Have expert knowledge of EDA tools and software-development methodologies.
• Understand custom analog development flows and software and hardware environments.
• Demonstrate efficient task analysis, pragmatic solution development, communication, problem-solving, and cross-functional collaboration.
• Be fluent in English.