Staff STA Engineer
Key Skills for This Role
Full Job Posting
Responsibilities
- Responsibilities
- STA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc…) Generating ECO for timing closure for complex multi power domain designs Good experience in running STA regression with high number of modes/corners efficiently. Power recovery with STA signoffDebug constraint issues in P&R environment LEC/Low power checks experience Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Strong in problem solving with deep understanding of technical issues. Candidate should have keen eye to improve existing flow and methods with positive impact on PPA.
- #LI-VS1
Qualifications
- Qualifications
- BE in Electrical Engineering or related + 6 years of experience, or M.Tech + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Solid track record of releasing complex ICs to market Ability to clearly articulate issues, challenges, and concerns to all levels of management Must have good written and verbal cross-functional communication skills
- #LI-VS1
More details about our company benefits can be found here
- https://www.onsemi.com/careers/career-benefits
About onsemi
Supplier of intelligent power and sensing technologies.
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