Staff STA Engineer

Role and product group

Responsibilities

• Lead STA work and handle timing constraints for full-chip I/O protocols such as I2C, DDR, and USB.
• Generate ECOs for timing closure in complex multi-power-domain designs.
• Run STA regression efficiently across numerous modes and corners.
• Perform power recovery with STA signoff and debug constraints in the P&R environment.
• Perform LEC and low-power checks.
• Use Verilog and scripting languages; improve existing flows and methods to positively affect PPA.
• Apply strong problem-solving skills and deep technical understanding.

Qualifications

• BE in Electrical Engineering or a related field plus 6 years of experience, or M.Tech plus 5 years of experience.
• Experience working on and leading digital design, architecture, and ASIC/mixed-signal chip development.
• Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis, P&R, and UPF.
• Solid understanding of Verilog, TCL, and Perl, Python, or XML programming languages.
• Track record of releasing complex ICs to market.
• Ability to articulate issues, challenges, and concerns to all levels of management; good written and verbal cross-functional communication skills.

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