Staff SoC Design Engineer

The Opportunity

SoC Subsystem Development & IP Integration

PPA Optimization & Timing Closure

What Success Looks Like

Required

Preferred

What We Offer

• In addition to a competitive salary, we offer a variety of benefits to support your needs. The benefits below reflect our India-based offerings; for roles in other locations, benefits vary and are shared during the hiring process. These include:
• Medical, dental, and vision insurance
• Equity with the business
• Paid Parental Leave
• PF Retirement Plan
• Flexible PTO
• Winter holiday shutdown
• Catered lunch each day in our office
• Downtown Pune office location, close to shops, cafes, and local amenities
• Collaborative, low-ego culture with significant ownership and impact
• A work culture focused on innovative disruption
• If this role resonates with you, we encourage you to apply even if your experience does not perfectly match every qualification. We value potential, curiosity, and a willingness to learn just as much as direct experience.

Equal Employment Opportunity

E-Verify and Right to Work Notices

Privacy

Qualifications

• Required
• BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
• Proficiency in SystemVerilog or Verilog.
• Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute).
• Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation.
• Experience in logic synthesis and performance modeling.
• Experience in FPGA design.
• Familiarity with automotive safety standards (ASIL) and hardware security standards.

Preferred Qualifications

• Preferred

Responsibilities

• Own SoC-level subsystem development and seamless integration with third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
• Contribute directly to the definition of the SoC architecture by deeply understanding its application requirements.
• Package designs for customer releases and rapidly iterate based on customer feedback.
• Own Power, Performance, and Area (PPA) optimization strategies at the SoC level.
• Apply low-power digital design techniques to optimize hardware efficiency.
• Contribute to timing closure across the full product lifecycle, spanning front-end, back-end, and final tapeout stages.
• Balance single-stream latency against scaled throughput performance.
• Within your first 6–12 months, you'll:
• Independently own SoC subsystem development and drive measurable PPA improvements.
• Develop an in-depth understanding of the architecture and software interfaces, enabling you to debug complex issues across the full SW/HW stack.
• Successfully package and deliver design releases for customer evaluation and integration.
• What We're Looking For
• BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience.
• Proficiency in SystemVerilog or Verilog.
• Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute).
• Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation.
• Experience in logic synthesis and performance modeling.
• Experience in FPGA design.
• Familiarity with automotive safety standards (ASIL) and hardware security standards.