Staff Design Verification Engineer
Role Overview
Own verification strategy and execution for complex out-of-order processors and cache or memory subsystems.
Drive verification of speculative execution, memory ordering, and coherence features from architecture through tape-out.
Key Skills for This Role
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About SiFive
SiFive develops RISC-V compute platforms for demanding applications across artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets.
The company emphasizes collaborative teams, processor innovation, and inclusive employment practices.
Role Overview
Own verification strategy and execution for complex out-of-order processors and cache or memory subsystems.
Drive verification of speculative execution, memory ordering, and coherence features from architecture through tape-out.
Verification Ownership
- Verify out-of-order front-end, back-end, retirement, recovery, and memory subsystems.
- Define test plans from ISA and microarchitecture specifications, including speculative execution, memory consistency, and coherence behavior.
- Drive functional, code, assertion, and scenario coverage closure to sign-off criteria.
Testbench and Modeling
- Architect constrained-random, coverage-driven UVM testbenches for processor pipelines, cache and memory hierarchies, TLBs, IOMMUs, and coherence protocols.
- Develop generators, monitors, scoreboards, and protocol checkers for out-of-order stress scenarios.
- Model ISA and memory behavior for checking instruction retirement, architectural state, fences, and atomic semantics.
Formal Verification and Debug
- Write assertions for deadlock, livelock, flush, replay, ordering, and data-bypass properties.
- Apply formal verification to reorder buffers, scoreboards, arbiters, FIFOs, coherence controllers, and TLB state machines.
- Lead debug of ordering violations, hazards, speculation issues, coherence races, TLB edge cases, and privilege interactions.
Methodology and Leadership
- Evolve design verification methodology with stress scenarios, memory models, and coherence checkers.
- Mentor junior design verification engineers and collaborate with architecture, design, software, and post-silicon teams.
Required Qualifications
- Bachelor’s, master’s, or doctoral degree in electrical engineering, computer engineering, computer science, or a related field.
- Typically 8+ years of ASIC, SoC, or IP design verification experience.
- Significant experience with out-of-order CPU or advanced core verification.
- Strong SystemVerilog and UVM expertise.
- Understanding of memory consistency models, coherence protocols, and cache hierarchies.
- Hands-on coverage-driven verification, assertion-based verification, and regression-debug experience.
Preferred Qualifications
- Experience verifying multicore out-of-order systems and inter-core coherence.
- Formal verification experience with out-of-order structures.
- Exposure to RISC-V or ARM instruction set and privilege specifications.
- Experience with performance verification or microarchitecture modeling.
- Technical leadership on complex CPU or SoC projects.
Additional Information
Employment is contingent on successful background and reference checks and satisfactory proof of the right to work in India.
Employment is also subject to authorization to access export-controlled technology or the company’s ability to obtain required approvals.
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