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Staff ATE Test Engineer

Google
Sunnyvale, USA
Senior · 10+ years experience
Onsite
USD 192000-278000 / year
Discovered 1 weeks ago

Full Job Posting

Responsibilities

  • Lead the development and architectural definition of silicon test requirements, driving strategic alignment across design teams, DFT engineers, and external vendors.
  • Define and direct broad strategies for SoC product NPI, bring-up, verification, characterization, and qualification, resolving complex issues across bench testing, test-coverage optimization, and system-to-ATE correlation.
  • Act as a domain expert in ATE testing, leveraging deep industry experience to establish technical standards, architect scalable test solutions, and mentor engineering teams to drive systemic quality improvements.
  • Influence and partner strategically with design, DFT, and quality teams to shape next-generation chip architectures, ensuring proactive "design-for-testability" and establishing industry-leading best practices for post-silicon testing.
  • Oversee and optimize the chip production life-cycle, driving continuous improvement initiatives for test program architecture, advanced volume data analytics, test time reduction, yield optimization, and complex Return Merchandise Authorization (RMA) failure analysis.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience in test engineering, product engineering or silicon quality/reliability.
  • Experience in ASIC or SoC test development, bring-up or debug.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with scan/ATPG test development or memory BIST test development and repair implementation.
  • Experience testing IPs such as Phase-Locked Loops (PLLs), PVT sensors, temperature sensors, Process Monitor Ring Oscillator (PMRO), and eFuse.
  • Experience with ATE probe card design and load board design.
  • Experience with UCIE, HBM, PCIE, DDR.
  • Extensive experience with Automatic Test Equipment (ATE) from Advantest and Teradyne (e.g., EXA scale, UltraFlex+).

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