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SoC DFT Engineer, Cloud

Google
Sunnyvale, USA
Senior · 10+ years experience
Onsite
USD 163000-236000 / year
Discovered 2 weeks ago

Full Job Posting

Responsibilities

  • Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
  • Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
  • Develop diagnostic databases, software and hardware for logic and memory fail debug.
  • Design and implement system level test strategy.
  • Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience in DFT architecture, implementation, and verification for SoCs.
  • Experience in silicon bring-up, debug, or validation of DFT features.
  • Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 10 years of experience in DFT architecture, implementation, and verification for SoCs.
  • Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
  • Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
  • Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
  • Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL).

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