{bc}
company_site

Silicon Engineer, Power Analysis, DeepMind

Google
California, USA
Senior · 7+ years experience
Onsite
USD 217000-236000 / year
Discovered 3 weeks ago
perl

Full Job Posting

Responsibilities

  • Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations.
  • Lead and drive the automation and integration of power analysis processes—including RTL power analysis, optimization, IP selection, physical design, and timing closure—into our automated flow.
  • Apply hardware expertise to build, create, and integrate software components for automated early- and late-stage power analysis and optimization.
  • Partner with systems power and cross-functional teams to define, execute, and advocate for power management and reduction methodologies from SoC architecture through sign-off.
  • Specify requirements for power management IPs while managing their design, integration, and post-silicon validation.
  • - Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations. - Lead and drive the automation and integration of power analysis processes—including RTL power analysis, optimization, IP selection, physical design, and timing closure—into our automated flow. - Apply hardware expertise to build, create, and integrate software components for automated early- and late-stage power analysis and optimization. - Partner with systems power and cross-functional teams to define, execute, and advocate for power management and reduction methodologies from SoC architecture through sign-off. Specify requirements for power management IPs while managing their design, integration, and post-silicon validation.

Minimum qualifications:

7 years of experience working in ASIC power analysis & optimization, including experience with production chips

Experience in tape-outs of chips

Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process

Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler)

Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows

Software development experience

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Physics or related field

Qualifications

  • Minimum qualifications: - 7 years of experience working in ASIC power analysis & optimization, including experience with production chips - Experience in tape-outs of chips - Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process - Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler) - Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows - Software development experience Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Physics or related field

Apply for this job in 1 click

Skip the repetitive application forms

Install the Base Career Chrome Extension and autofill job applications across major job boards with your profile.

Sarah M.James T.Maya R.

Trusted by over 500,000 job seekers on Base Career

Start Free Today

More from this employer

More jobs at Google