Senior Verification Engineer - ARM Fabric Unit Level

You will develop UVM-based verification test benches and methodologies. These will verify our in house ARM architecture based distributed fabric needed to transport control, sidebands and data as needed.

During the course of a project, you will drive the following aspects of verification for your unit:

Architect the testbenches and craft verification environment using SV and UVM methodology

Define test plans, tests and verification infrastructure for modules, clusters and systems

Build efficient and reusable bus functional models, monitors, checkers, and scoreboards

Implement functional coverage and coordinate the verification closure process for the unit

Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust

BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification.

Proven experience in ARM architecture and protocols (AXI, AHB and APB)

Experience in the latest verification methodologies like SV and UVM

Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug

Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization

Exposure on using AI (like Claude or Cursor) extensively for code development would be a big plus

A mentality towards constant improvement and looking to build a multiplier effect through your work and automation

Exposure to Formal verification would be excellent

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