Senior Technical Architect (US)

Job Summary

Key Responsibilities

• Candidates with 8 to 14 years' experience is mandatory
• Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),
• Electrical Engineering (EE), VLSI Design, or a closely related field" Define ASIC/SoC verification strategy:
• Good understanding of ASIC/SoC life cycle
• Full chip testplan development:
• Has participated in multiple ASIC/SoC verification till tapeout stage
• Full chip TB Architecture definition
• Experience writing ASIC/SoC testplans
• UVM based testbench development
• 1.Experience in ASIC/SoC Testbench definition
• 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
• SV functional coverage, Assertions coding
• 1.Expertise & hands-on experience in OVM/UVM methodologies using SV
• 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
• C based TB development
• Experience in developing TB components for SOC with C, SV
• Test case development, coding, execution, bug analysis
• Experience in developing TB components, including functional coverage implementation and assertion coding
• Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
• 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
• Experience in SOC C based tests coding & debugging
• Gate Level Simulation
• Experience in Gate level simulation & netlist debugging
• Regressions, coverage analysis
• Experience in regression failure analysis, Functional and Code Coverage closure
• Own and execute verification closure
• Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.
• Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.
• Experience in Document test plans, micro-architecture specifications, and verification results for team reviews
• Core Technical Skills
• Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.
• Expert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).
• Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
• Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable."
• Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.
• Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
• Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.
• Soft Skills
• Strategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.
• Influence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.
• Electrical Engineering (EE), VLSI Design, or a closely related field"
• Define ASIC/SoC verification strategy:
• Experience in ASIC/SoC Testbench definition
• Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
• Expertise & hands-on experience in OVM/UVM methodologies using SV
• Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

Qualifications

• Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
• Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
• Experience in SOC C based tests coding & debugging
• Gate Level Simulation
• Experience in Gate level simulation & netlist debugging
• Regressions, coverage analysis
• Experience in regression failure analysis, Functional and Code Coverage closure
• Own and execute verification closure
• Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.
• Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.
• Experience in Document test plans, micro-architecture specifications, and verification results for team reviews
• Core Technical Skills
• Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.
• Expert Languages: Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).
• Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
• Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable."
• Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.
• Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."
• Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.
• Soft Skills
• Strategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.
• Influence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.
• Skill Requirements
• Other Requirements