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Senior Standard Cell Design Engineer

JRC Careers
USA
Senior · 5+ years experience
Onsite
Discovered 2 weeks ago
Python

Full Job Posting

🧠What You Bring

  • Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
  • Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
  • Deep knowledge of semiconductor design methodologies and principles.
  • Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
  • Demonstrated experience being involved in test-chip designs and MPW execution.
  • Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
  • Extensive experience with simulation tools, specifically for library characterization.
  • ⭐Bonus Points
  • Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
  • Hands‐on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design‐rule familiarity.
  • Proven background in SRAM/NVM bitcell design and/or memory compiler development.
  • Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
  • Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).
  • At JRC we offer...
  • A competitive compensation package
  • An exceptional employee benefits program, providing support for our team members' well-being and success
  • The chance to contribute to a high-profile Department of Defense programs and make a positive impact
  • A collaborative work environment where teamwork, creativity, and innovation thrive
  • Opportunities for professional growth and development, helping you advance your career

Qualifications

  • Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
  • Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
  • Deep knowledge of semiconductor design methodologies and principles.
  • Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
  • Demonstrated experience being involved in test-chip designs and MPW execution.
  • Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
  • Extensive experience with simulation tools, specifically for library characterization.
  • Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
  • Hands‐on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design‐rule familiarity.
  • Proven background in SRAM/NVM bitcell design and/or memory compiler development.
  • Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
  • Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).
  • At JRC we offer...
  • A competitive compensation package
  • An exceptional employee benefits program, providing support for our team members' well-being and success
  • The chance to contribute to a high-profile Department of Defense programs and make a positive impact
  • A collaborative work environment where teamwork, creativity, and innovation thrive
  • Opportunities for professional growth and development, helping you advance your career

Preferred Qualifications

  • ⭐Bonus Points

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