Senior Silicon Validation Engineer

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

CI2 Platform Enablement is charged with helping bring our custom ASIC's from concept through to production.

In pre-silicon, we support integration and test on our hardware emulation platforms, and in post-silicon we help develop tests, operate bringup and validation efforts, and ensure our custom ASIC systems are qualified and sustainable.

We own and deliver the Silicon Validation effort of our overall silicon product development lifecycle. Efforts may center on power features, interfaces, HBM memory, compute functionality, and/or various aspects of system performance.

You will develop and execute test plans, characterize and enable silicon, and investigate and resolve chip and system issues.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Own the bringup and New Product Introduction (NPI) phases to enable custom silicon products, validating ASIC subsystems such as boot, PCIe, memory (e.g., HBM, SRAM), compute cores, and power.
• Design, develop, operate, and maintain detailed validation tests and test plans in coordination with cross-functional architecture, design, and software teams.
• Perform system characterization, qualification, and debugging to root-cause failures across both pre-silicon prototyping platforms and post-silicon production.
• Provide feedback to improve critical features like power management quality, performance, and reliability through successive generations of designs.
• Partner with customers, systems, manufacturing, diagnostics, and vendor teams to resolve issues and eliminate failures by "shifting left" in the production and deployment lifecycle.

Qualifications

• Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with hardware engineering, ASIC digital design, design validation, test planning, and test design. Preferred qualifications:
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
  • Experience with silicon validation, New Product Introduction (NPI), and the bring-up, characterization, and qualification of custom silicon.
  • Experience collaborating with cross-functional systems, hardware, manufacturing, and vendor teams to drive the bring-up, qualification, and deployment of custom silicon.
  • Experience with platform accelerators, high-speed ASIC interfaces, compute, memory systems (e.g. HBM), Design for Testing, and power system features for high-power SoCs.